At the present time, electronic products are used in almost every aspect of life, and at the heart of these electronic products is the integrated circuit. Integrated circuits can be used in computers, cell-phones, televisions, digital cameras and even airplanes.
Integrated circuits are made in and on semiconductor wafers by extremely complex manufacturing methods that require the coordination of hundreds or even thousands of precisely controlled process steps. Once completed, each semiconductor wafer can have hundreds to tens of thousands of integrated circuits.
Integrated circuits are made up of hundreds to millions of individual components. Typical individual components may include active and passive devices. By way of example, one common active component is a semiconductor transistor and one common passive component is a capacitor. The most common and important semiconductor material employed is silicon, and some of the most preferred silicon-based semiconductor components are built of complementary metal oxide semiconductor (“CMOS”) transistors.
CMOS components include both an n-channel metal-oxide semiconductor field-effect transistor (“MOSFET”) and a p-channel MOSFET combined on a single silicon wafer. CMOS technology offers lower power consumption than other metal-oxide semiconductor technologies, since power is consumed only during the logic switching cycle and not in static conditions.
Improvements to current CMOS technology include using an insulating substrate (e.g.—silicon on insulator) and introducing strain or stress within the channel region of each n-channel and p-channel MOSFET. It is generally known that the stresses in MOSFET channels and the accompanying stress-induced carrier mobility increase can be altered by varying the thickness of the strained elements located in the adjacent source/drain regions. For example, by increasing the thickness of the strained elements located adjacent the channel region (i.e.—the source/drain regions) the drive current (Ion) of a MOSFET device may be increased. Unfortunately, for silicon on insulator technology, the thickness of the strained elements is naturally limited by the thickness of the silicon layer formed over the insulating layer.
Furthermore, one of the major drawbacks of improving Ion (e.g.—by increasing the thickness of the silicon on insulator layer), is that a thicker silicon on insulator layer results in higher device leakage current (Ioff) (e.g.—higher source/drain leakage currents). Regrettably, increases in Ioff due to thicker silicon on insulator layers negatively affect the ratio of (Ion/Ioff), which is a common standard used to measure MOSFET performance.
Consequently, additional methods have been developed to enhance the ratio of (Ion/Ioff). One such method increases stresses within the MOSFET channel region by positioning the strained source/drain elements closer to the channel regions of the MOSFET. Unfortunately, the potential of this approach has been exploited to its limit and further enhancement of the proximity effect between the MOSFET channel and the strained MOSFET source/drain regions raises the gate leakage current to an unacceptable level.
Thus, a need still remains for a reliable integrated circuit and method of fabrication, wherein the integrated circuit realizes enhanced device drive current while minimizing device leakage current. In view of the ever-increasing commercial competitive pressures, increasing consumer expectations, and diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Moreover, the ever-increasing need to save costs, improve efficiencies, and meet such competitive pressures adds even greater urgency to the critical necessity that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.